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vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 1 01/05/01 ? vitesse semiconductor corporation ? 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com features general description the VSC8163 is a 16:1 multiplexer with integrated clock generator for use in sonet/sdh systems oper- ating at a 2.48832gb/s data rate. the internal clock generator uses a phase-locked loop (pll) to multiply either a 77.76mhz or 155.52mhz reference clock in order to provide the 2.48832ghz clock for internal logic and output retiming. the 16-bit parallel interface incorporates an on-board fifo, eliminating loop timing design issues by providing a flexible parallel timing architecture. the device operates using a +3.3v power sup- ply, and is packaged in a thermally-enhanced plastic package. the thermal performance of the 128pqfp allows the use of the VSC8163 without a heat sink under most thermal conditions. VSC8163 block diagram ? 2.488gb/s 16:1 multiplexer targeted for sonet oc-48 / sdh stm-16 applications differential lvpecl low-speed interface on-chip pll-based clock generator 128 pin, 14x20mm pqfp package single +3.3v supply d0- d0+ d15- d15+ clk16o- input register output retime 2.488ghz pll refclk refclk+ clk16o+ do- do+ 16x5 fifo clk16i- clk16i+ write pointer read pointer fifo control reset divide by 16 fifo_warn clko+ clko- ref_freqsel refclko- refclko+ divide by 2
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 2 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com functional description low-speed interface the upstream device should use the clk16o as the timing source for its final output latch (see figure 1). the upstream device should then generate a clk16i phase aligned with the data. the VSC8163 will latch d[15:0] on the rising edge of clk16i+. the data must meet setup and hold times with respect to clk16i (see table 2). in addition to the clk16o clock output, there also exists a utility refclko output signal, which is a clock with the same rate as that presented at the refclk input. a fifo exists within the VSC8163 to eliminate difficult system loop timing issues. once the pll has locked to the reference clock, reset must be held low for a minimum of five clk16 cycles ( > 32ns) to ini- tialize the fifo, then reset should be set high and held constant for continuous fifo operation. for the transparent mode of operation (no fifo), simply hold reset at a constant low state (see figure 2). the use of a fifo permits the system designer to tolerate an arbitrary amount of delay between clk16o and clk16i. once reset is asserted and the fifo initialized, the delay between clk16o and clk16i can decrease or increase up to one period of the low-speed clock (6.4ns). should this delay drift exceed one period, the write pointer and the read pointer could point to the same word in the fifo, resulting in a loss of transmitted data (a fifo overflow). in the event of a fifo overflow, an active low fifo_warn signal is asserted (for a minimum of 5 clk16i cycles) which can be used to initiate a reset signal from an external controller. the clk16o output driver is a lvpecl output driver designed to drive a 50 ? transmission line. the transmission line can be dc terminated with a split-end termination scheme (see figure 3), or dc terminated by 50 ? to v cc -2v on each line (see figure 4). at any time, the equivalent split-end termination technique can be substituted for the traditional 50 ? to v cc -2v on each line. ac-coupling can be achieved by a number of meth- ods. figure 5 illustrates an example ac-coupling method for the occasion when the downstream device pro- vides the bias point for ac-coupling. if the downstream device were to have internal termination, the line-to- line 100 ? resistor may not be necessary. figure 1: low-speed systems interface refclk 2.488ghz pll divide by 16 clk16o x16 16 x 5 fifo VSC8163 clk16i upstream device write read
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 3 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 2: enabling fifo operation figure 3: split-end dc termination of clk16o+/-, refclko+/- figure 4: traditional dc termination of clk16o+/-, refclko+/- minimum 5 clk16 cycles (32ns) fifo mode operation transparent mode operation holding reset ? low ? for a minimum of five clk16 cycles, then setting ? high ? enables fifo operation. holding reset constantly ? low ? bypasses the fifo for transparent mode operation. pll locked to reference clock. reset VSC8163 r2 r2 z o z o r1 r1 v ee v cc v cc r2 + v ee r1 r1+r2 = v term r1 || r2 = z 0 split-end equivalent termination is z 0 to v term r1 = 125 ? r2 = 83 ? , zo=50 ? , v term = v cc -2v VSC8163 50 ? 50 ? v cc -2v z 0 z 0
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 4 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 5: ac termination of clk16o+/-, refclko+/- high-speed data and clock output the high-speed data and clock output drivers consist of a differential pair designed to drive a 50 ? transmis- sion line. the transmission line should be terminated with a 100 ? resistor at the load between true and comple- ment outputs (see figure 6). connection to a termination voltage is not required. the output driver is back terminated to 50 ? on-chip, providing a snubbing of any reflections. if used single-ended, the high-speed output driver must still be terminated differentially at the load with a 100 ? resistor between true and complement out- puts. the high-speed clock output can be powered down for additional power savings. to power down the high- speed clock, tie the associated pins to v cc (see table 3, package pin descriptions, pins 5,6,7). figure 6: high-speed output termination VSC8163 100nf 50 ? 50 ? z 0 z 0 100nf v cc -2v downstream bias point generated internally v cc v ee z 0 = 50 ? 50 ? 100 ? 50 ? pre-driver
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 5 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com clock generator an on-chip pll generates the 2.48832ghz transmit clock from the externally provided refclk input. the on-chip pll uses a low phase noise reactance-based voltage controlled oscillator (vco) with an on-chip loop filter. the loop bandwidth of the pll is within the sonet specified limit of 2mhz. the customer can select to provide either a 77.76mhz reference (recommended), or the 2x of that refer- ence, 155.52mhz. ref_freqsel is used to select the desired reference frequency. ref_freqsel = ? 0 ? designates refclk input as 77.76mhz, ref_freqsel = ? 1 ? designates refclk input as 155.52mhz. the refclk should be of high quality since noise on the refclk below the loop band width of the pll will pass through the pll and appear as jitter on the output. preconditioning of the refclk signal with a vcxo may be required to avoid passing refclk noise with greater than 2ps of rms jitter to the output. the VSC8163 will output the refclk noise in addition to the intrinsic jitter from the VSC8163 itself during such conditions. figure 7: ac termination of low-speed lvpecl refclk, d[15:0] inputs low-speed inputs the incoming low-speed data and reference clock input are received by lvpecl inputs d[15:0] and ref- clk. off-chip termination of these inputs is required. for ac-coupling, a bias voltage suitable for ac-cou- pling needs to be provided (see figure 7 for external biasing resistor scheme). in most situations these inputs will have high transition density and little dc offset. however, in cases where this does not hold, direct dc connection is possible. all serial data inputs have the same circuit topology, as shown in figure 7. if the input signal is driven differentially and dc-coupled to the part, the mid-point of the v cc = 3.3v v ee = 0v c in chip boundary z o c in typ = 100nf for ac operation r2 r1 v cc v ee c in z o r2 r1 v cc v ee split-end equivalent termination is z 0 to v term r1 = 83 ? r2 = 125 ? , z 0 =50 ? , v term = v cc -2v v cc r2 + v ee r1 r1+r2 = v bias r1 || r2 = z o
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 6 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com input signal swing should be centered about this common-mode reference voltage ( v cmi ) and not exceed the maximum allowable amplitude. for single-ended, dc-coupling operations, it is recommended that the user pro- vides an external reference voltage. the external reference should have a nominal value equivalent to the com- mon mode switch point of the dc-coupled signal, and can be connected to either side of the differential gate. power supplies this device is specified as a lvpecl device with a single positive 3.3v supply. should the user desire to use the device in an ecl environment with a negative 3.3v supply, then v cc will be ground and v ee will be -3.3v. if used with v ee tied to -3.3v, the ttl control signals are still referenced to v ee . decoupling of the power supplies is a critical element in maintaining the proper operation of the part. it is recommended that the v cc power supply be decoupled using a 0.1 f and 0.01 f capacitor placed in parallel on each v cc power supply pin as close to the package as possible. if room permits, a 0.001 f capacitor should also be placed in parallel with the 0.1 f and 0.01 f capacitors mentioned above. recommended capacitors are low inductance ceramic smt x7r devices. for the 0.1 f capacitor, a 0603 package should be used. the 0.01 f and 0.001 f capacitors can be either 0603 or 0402 packages. extra care needs to be taken when decoupling the analog power supply pins (v ccana ). in order to maintain the optimal jitter and loop bandwidth characteristics of the pll contained in the VSC8163, the analog power supply pins should be filtered from the main power supply with a 10 h c-l-c pi filter. if preferred, a ferrite bead may be used to provide the isolation. the 0.1 f and 0.01 f decoupling capacitors are still required and must be connected to the supply pins between the device and the c-l-c pi filter (or ferrite bead). for low frequency decoupling, 47 f tantalum low inductance smt caps are sprinkled over the board ? s main +3.3v power supply and placed close to the c-l-c pi filter. if the device is being used in an ecl environment with a -3.3v supply, then all references to decoupling v cc must be changed to v ee , and all references to decoupling 3.3v must be changed to -3.3v. figure 8: pll power supply decoupling scheme 10f 0.1f 10h v ee v ee_ana v cc_ana v cc 0.01f 0.1f
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 7 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com ac characteristics figure 9: parallel input data and clock timing waveforms figure 10: serial data and clock output phase timing waveforms t txdsu t txdh valid data 1 clk16i+ parallel data clock input d[0...15]+ parallel data inputs clk16o+ parallel data clock output = don't care valid data 2 d15 msb lsb time d14 d13 do+ differential serial data output clko+ differential clock output note: bit 15 (msb) is received first, bit 0 (lsb) is received last. clko per d1 d0 t hold t set
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 8 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com table 1: ac characteristics parameters description min typ max units conditions t dsu data setup time to the rising edge of clk16i+ 0.75 ?? ns t dh data hold time after the rising edge of clk16+ 1.0 ?? ns t dor ,t dof do rise and fall time ?? 120 ps 20% to 80% into 100 ? load see figure 6 t clkr , t clkf clk16o rise and fall times ?? 250 ps see figures 3 and 4 clk16o d clk16o duty cycle 40 ? 60 % clki d clk16i duty cycle 30 ? 70 % assuming 10% distortion of clko rck d reference clock duty cycle 40 ? 60 % clko d clko duty cycle 40 ? 60 % clko per clko period ? 401.9 ? ps sonet based 77.76mhz or 155.52mhz reference clock clk16o per clk16o period ? 6.4 ? ns sonet based 77.76mhz or 155.52mhz reference clock t set do setup time with respect to rising clko edge ? 90 ? ps inverting clko will switch (approx) t set and t hold values. t hold do hold time with respect to rising clko edge ? 310 ? ps inverting clko will switch (approx) t set and t hold values. clock multiplier performance t dj output data jitter ?? 4ps rms, tested to sonet specification (12khz to 20mhz) with 2ps rms jitter on refclk. t cj output clock jitter ?? 4ps rms, tested to sonet specification (12khz to 20mhz) with 2ps rms jitter on refclk. jitter tol jitter tolerance ???? exceeds sonet/sdh mask tuning range -100 +100 ppm
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 9 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 11: differential and single-ended input / output voltage measurement table 2: dc characteristics (over recommended operating conditions) parameters description min typ max units conditions v oh(do) output high voltage (do) v cc - 0.825 ? v cc v see figure 12 v ol(do) output low voltage (do) v cc - 1.30 ? v cc - 0.50 v see figure 12 ? v od(do) data output differential voltage (do) 550 ? 900 mv 100 ? termination between do at load ? v oclk(clko) clk output differential voltage (clko) 500 ? 900 mv 100 ? termination between do at load v cmo output common-mode voltage 2.10 ? 3.00 v r do back termination impedance 40 ? 60 ? guaranteed, not tested v oh output high voltage (clk16o, refclko) v cc - 1.020 ? v cc - 0.700 v see figure 12 v ol output low voltage (clk16o, refclko) v cc - 2.000 ? v cc - 1.620 v see figure 12 v ih input high voltage (lvpecl) v cc - 1.100 ? v cc - 0.700 v v il input low voltage (lvpecl) v cc - 2.0 ? v cc - 1.540 v i ih input high current (lvpecl) ?? 200 a v in =v ih (max) i il input low current (lvpecl) -50 ?? a v in =v il (min) r i input resistance (lvpecl) 10k ?? ? ? v i input differential voltage (lvpecl) 200 ?? mv v cmi input common-mode voltage (lvpecl) v cc - 1.5 ? v cc - 0.5 v v oh output high voltage (ttl) 2.4 ?? vi oh = -1.0ma v ol output low voltage (ttl) ?? 0.5 v i ol = +1.0ma v ih input high voltage (ttl) 2.0 ? 5.5 v single ended swing differential swing = = a a b differential swing is specified as equal in magnitude to single ended swing. b * differential swing ( ) is specified as | b - a | ( or | a - b | ), as is the single ended swing.
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 10 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 12: parametric measurement information v il input low voltage (ttl) 0.0 ? 0.8 v i ih input high current (ttl) ?? 500 a v in = 2.4v i il input low current (ttl) ?? -500 a v in = 0.4v v cc supply voltage 3.14 ? 3.47 v 3.3v 5% p d power dissipation ? 1.2 1.7 w outputs open, v cc = v cc max i cc supply current ? 350 490 ma outputs open, v cc = v cc max parameters description min typ max units conditions pecl rise and fall time serial output load t r t f 80% 20% z 0 = 5 0? 50 ? v cc -2v parametric test load circuit high-speed data output z 0 = 5 0? 50 ? v cc parametric test load circuit
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 11 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com absolute maximum ratings (1) power supply voltage (v cc ).......................................................................................................... -0.5v to +3.8v dc input voltage (differential inputs).................................................................................... -0.5v to v cc +0.5v dc input voltage (ttl inputs) .................................................................................................. .... -0.5v to +5.5v dc output voltage (ttl outputs) ........................................................................................ -0.5v to v cc + 0.5v output current (ttl outputs) ................................................................................................... .............. +/-50ma output current (differential outputs).......................................................................................... .............. +/-50ma case temperature under bias .................................................................................................... ..-55 o c to +125 o c recommended operating conditions power supply voltage, (v cc )................................................................................................................ +3.3v+ 5% operating temperature range ........................................................... 0 o c ambient to +85 o c case temperature note: (1) caution: stresses listed under ?absolute maximum ratings? may be applied to devices one at a time without caus- ing permanent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability. esd ratings proper esd procedures should be used when handling this product. the VSC8163 is rated to the following esd voltages based on the human body model: 1. all pins are rated at or above 1500v.
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 12 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com package pin descriptions figure 13: pin diagram?128-pin pqfp VSC8163 nc nc nc vcc veep_clk veep_clk veep_clk vcc clko+ clko- vcc vcc nc nc vee vee vee vcc do+ do? vcc nc vcc vcc vcc vee vee vee vee vee nc nc nc nc nc nc nc ref_freqsel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vcc d13+ d13? vcc d12+ d12? vee d11+ d11? vcc d10+ d10? vcc d9+ d9? vee d8+ d8? vcc d7+ d7? vcc d6+ d6? vee d5+ d5? vcc d4+ d4? vcc d3+ d3? vee d2+ d2? vcc nc 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 vcc vee fifo_warn vee vcc reset nc nc nc nc nc vcc vee clk16o+ clk16o? vcc clki+ clki? vee d0? d0+ vcc d1? d1+ nc vcc vcc vee vee nc nc vcc_ana vee_ana refclko? refclko+ vee vcc refclk? refclk+ nc nc nc nc nc vee d15+ d15? vcc d14+ d14? nc vcc 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 13 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com package pin descriptions table 3: package pin identification pin # name i/o level description 1nc ?? no connect, leave unconnected (1) 2nc ?? no connect, leave unconnected (1) 3nc ?? no connect, leave unconnected (1) 4vcc ? +3.3v typ. positive power supply 5veep_clk ? gnd typ. high-speed clock v ee power supply (tie to v cc for power down) 6veep_clk ? gnd typ. high-speed clock v ee power supply (tie to v cc for power down) 7veep_clk ? gnd typ. high-speed clock v ee power supply (tie to v cc for power down) 8vcc ? +3.3v typ. positive power supply 9 clko+ o hs high-speed clock output, true 10 clko- o hs high-speed clock output, complement 11 vcc ? +3.3v typ. positive power supply 12 vcc ? +3.3v typ. positive power supply 13 nc ?? no connect, leave unconnected (1) 14 nc ?? no connect, leave unconnected (1) 15 vee ? gnd typ. negative power supply 16 vee ? gnd typ. negative power supply 17 vee ? gnd typ. negative power supply 18 vcc ? +3.3v typ. positive power supply 19 do+ o hs high-speed data output, true 20 do- o hs high-speed data output, complement 21 vcc ? +3.3v typ. positive power supply 22 nc ?? no connect, leave unconnected (1) 23 vcc ? +3.3v typ. positive power supply 24 vcc ? +3.3v typ. positive power supply 25 vcc ? +3.3v typ. positive power supply 26 vee ? gnd typ. negative power supply 27 vee ? gnd typ. negative power supply 28 vee ? gnd typ. negative power supply 29 vee ? gnd typ. negative power supply 30 vee ? gnd typ. negative power supply 31 nc ?? no connect, leave unconnected (1)
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 14 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com 32 nc ?? no connect, leave unconnected (1) 33 nc ?? no connect, leave unconnected (1) 34 nc ?? no connect, leave unconnected (1) 35 nc ?? no connect, leave unconnected (1) 36 nc ?? no connect, leave unconnected (1) 37 nc ?? no connect, leave unconnected (1) 38 ref_freqsel i ttl reference clock input select 39 vcc ? +3.3v typ. positive power supply 40 vee ? gnd typ. negative power supply 41 fifo_warn o ttl fifo overflow warning 42 vee ? gnd typ. negative power supply 43 vcc ? +3.3v typ. positive power supply 44 reset i ttl reset to align fifo write and read pointers 45 nc ?? no connect, leave unconnected (1) 46 nc ?? no connect, leave unconnected (1) 47 nc ?? no connect, leave unconnected (1) 48 nc ?? no connect, leave unconnected (1) 49 nc ?? no connect, leave unconnected (1) 50 vcc ? +3.3v typ. positive power supply 51 vee ? gnd typ. negative power supply 52 clk16o+ o lvpecl low-speed clock output, true. a divide-by-16 version of the 2.48832ghz pll. 53 clk16o- o lvpecl low-speed clock output, complement. a divide-by-16 version of the 2.48832ghz pll. 54 vcc ? +3.3v typ. positive power supply 55 clki+ i lvpecl low-speed clock input for latching low-speed data, true 56 clki- i lvpecl low-speed clock input for latching low-speed data, complement 57 vee ? gnd typ. negative power supply 58 d0- i lvpecl low-speed differential parallel data (msb) 59 d0+ i lvpecl low-speed differential parallel data (msb) 60 vcc ? +3.3v typ. positive power supply 61 d1- i lvpecl low-speed differential parallel data 62 d1+ i lvpecl low-speed differential parallel data 63 nc ?? no connect, leave unconnected (1) pin # name i/o level description
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 15 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com 64 vcc ? +3.3v typ. positive power supply 65 nc ?? no connect, leave unconnected (1) 66 vcc ? +3.3v typ. positive power supply 67 d2- i lvpecl low-speed differential parallel data 68 d2+ i lvpecl low-speed differential parallel data 69 vee ? gnd typ. negative power supply 70 d3- i lvpecl low-speed differential parallel data 71 d3+ i lvpecl low-speed differential parallel data 72 vcc ? +3.3v typ. positive power supply 73 d4- i lvpecl low-speed differential parallel data 74 d4+ i lvpecl low-speed differential parallel data 75 vcc ? +3.3v typ. positive power supply 76 d5- i lvpecl low-speed differential parallel data 77 d5+ i lvpecl low-speed differential parallel data 78 vee ? gnd typ. negative power supply 79 d6- i lvpecl low-speed differential parallel data 80 d6+ i lvpecl low-speed differential parallel data 81 vcc ? +3.3v typ. positive power supply 82 d7- i lvpecl low-speed differential parallel data 83 d7+ i lvpecl low-speed differential parallel data 84 vcc ? +3.3v typ. positive power supply 85 d8- i lvpecl low-speed differential parallel data 86 d8+ i lvpecl low-speed differential parallel data 87 vee ? gnd typ. negative power supply 88 d9- i lvpecl low-speed differential parallel data 89 d9+ i lvpecl low-speed differential parallel data 90 vcc ? +3.3v typ. positive power supply 91 d10- i lvpecl low-speed differential parallel data 92 d10+ i lvpecl low-speed differential parallel data 93 vcc ? +3.3v typ. positive power supply 94 d11- i lvpecl low-speed differential parallel data 95 d11+ i lvpecl low-speed differential parallel data 96 vee ? gnd typ. negative power supply 97 d12- i lvpecl low-speed differential parallel data pin # name i/o level description
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 16 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com note: (1) no connect (nc) pins must be left unconnected, or floating. connecting any of these pins to either the positive or ne gative power supply rails may cause improper operation or failure of the device or in extreme cases, cause permanent damage to the device. 98 d12+ i lvpecl low-speed differential parallel data 99 vcc ? +3.3v typ. positive power supply 100 d13- i lvpecl low-speed differential parallel data 101 d13+ i lvpecl low-speed differential parallel data 102 vcc ? +3.3v typ. positive power supply 103 vcc ? +3.3v typ. positive power supply 104 nc ?? no connect, leave unconnected (1) 105 d14- i lvpecl low-speed differential parallel data 106 d14+ i lvpecl low-speed differential parallel data 107 vcc ? +3.3v typ. positive power supply 108 d15- i lvpecl low-speed differential parallel data (lsb) 109 d15+ i lvpecl low-speed differential parallel data (lsb) 110 vee ? gnd typ. negative power supply 111 nc ?? no connect, leave unconnected (1) 112 nc ?? no connect, leave unconnected (1) 113 nc ?? no connect, leave unconnected (1) 114 nc ?? no connect, leave unconnected (1) 115 nc ?? no connect, leave unconnected (1) 116 refclk+ i lvpecl reference clock input, true 117 refclk- i lvpecl reference clock input, complement 118 vcc ? +3.3v typ. positive power supply 119 vee ? gnd typ. negative power supply 120 refclko+ o lvpecl reference clock output, true 121 refclko- o lvpecl reference clock output, complement 122 vee_ana ? gnd typ. negative power supply pins for analog parts of cmu 123 vcc_ana ? +3.3v typ. positive power supply pins for analog parts of cmu 124 nc ?? no connect, leave unconnected (1) 125 nc ?? no connect, leave unconnected (1) 126 vee ? gnd typ. negative power supply 127 vee ? gnd typ. negative power supply 128 vcc ? +3.3v typ. positive power supply pin # name i/o level description
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 17 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com package information standoff lead coplanarity max. 0.17 .25 a l a 1 a 1 a 2 r1 r 1 b e a 10 typ. 10 typ. top view exposed heatsink exposed intrusion 0.127 max. rad. 2.92 .50 (2) 2.54 .50 pin 128 pin 1 e 1 e d 1 d notes: 1) drawing is not to scale 2) all dimensions in mm 3) package represented is also used for the 64, 80, & 100 pqfp packages. pin count drawn does not reflect the 128 package. pin 38 pin 64 pin 102 notes: 128-pin pqfp package drawing package #: 101-322-5 issue #: 2 key mm tol erance a2.35 max a1 0.25 max a2 2.00 +.10 d 17.20 .20 d1 14.00 .10 e 23.20 .20 e1 20.00 .10 l.88+.15/-.10 e.50basic b .22 .05 0 -7 r.30 typ r1 .20 typ
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 18 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com thermal considerations this package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. the thermal resistance is shown in the following table table 4: thermal resistance thermal resistance with airflow shown in the table 5 is the thermal resistance with airflow. this thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. the temperature dif- ference between the ambient airflow temperature and the case temperature should be the worst-case power of the device multiplied by the thermal resistance. table 5: thermal resistance with airflow maximum ambient temperature without heatsink the worst case ambient temperature without use of a heatsink is given by the equation: where: ca theta case-to-ambient at appropriate airflow a(max) ambient air temperature c(max) case temperature (85 o c for VSC8163) p (max) power (1.7w for VSC8163) symbol description c/w jc thermal resistance from junction-to-case. 1.34 ca thermal resistance from case-to-ambient with no airflow, including conduction through the leads. 25.0 airflow ca ( o c/w ) 100 lfpm 21 200 lfpm 18 400 lfpm 16 600 lfpm 14.5 t amax () t cmax () p ? max () ca =
vitesse semiconductor corporation preliminary data sheet VSC8163 oc-48 16:1 sonet/sdh mux with clock generator g52216-0, rev 3.3 page 19 01/05/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com the results of this calculation are listed in table 6: table 6: maximum ambient air temperature without heatsink note that ambient air temperature varies throughout the system based on the positioning and magnitude of heat sources and the direction of air flow. ordering information the order number for this product is formed by a combination of the device number, and package type. airflow max ambient temp( o c) none 43 100 lfpm 49 200 lfpm 54 400 lfpm 58 600 lfpm 60 VSC8163 xx device type VSC8163: oc-48 16:1 sonet/sdh package style qr: 128-pin pqfp mux with clock generator notice vitesse semiconductor corporation ( ? vitesse ? ) provides this document for informational purposes only. this document contains pre-production information about vitesse products in their concept, development and/or testing phase. all information in this document, includ ing descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. n othing contained in this document shall be construed as extending any warranty or promise, express or implied, that any vitesse product will be availabl e as described or will be suitable for or will accomplish any particular task. vitesse products are not intended for use in life support appliances, devices or systems. use of a vitesse product in such appl ications without writ- ten consent is prohibited.
vitesse semiconductor corporation VSC8163 oc-48 16:1 sonet/sdh mux with clock generator preliminary data sheet page 20 g52216-0, rev 3.3 01/05/00 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com

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